Designing the Future of AI Infrastructure with UALink
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Event hosted by Synopsys Inc
July 29, 2025 – July 29, 2025Online event
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Join us for an exclusive session where industry leaders from Astera Labs, AMD, and Synopsys delve into the recently announced UALink 200G 1.0 Specification.
This open standard opens new opportunities for AI interconnects with high-bandwidth, low-latency communication, enabling up to 1,024 accelerators within a single AI computing pod. UALink achieves Ethernet-like speeds with PCIe-level latency, pushing data center infrastructures to a new level.
Don't miss this opportunity to hear from the experts shaping the future of AI infrastructure and learn about its impact on power savings, architectural opportunities, design challenges, and ecosystem implementation insights from switch, accelerator, and IP industry leaders.